Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge which represents an information to be stored, and an access transistor which is connected with the storage capacitor. The access transistor includes a first and a second source/drain region, a channel connecting the first and the second source/drain region as well as a gate electrode controlling an electrical current flow between the first and second source/drain region. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of a word line and is electrically insulated from the channel by a gate insulating layer. By addressing the access transistor via a corresponding wordline, the information stored in the storage capacitor is read out. In particular, the information is read out to a corresponding bitline via a bitline contact.
In conventional DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends in the substrate in a direction perpendicular to the substrate surface.
According to another implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate. Generally, attempts have been made at further shrinking the area needed for a DRAM memory cell. At the same time, it is desirable to obtain optimum characteristics of the access transistor.
Accordingly, an improved transistor as well as an improved method of manufacturing such a transistor is needed. In addition, an improved memory cell array as well as an improved method of forming such a memory cell array is needed.